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Chips&Media is the industry’s leading provider of video cores offering high performance video encode and decode acceleration to a wide range of key consumer electronics markets.
Video IP / CODA9 FHD SERIES / CODA988
CODA988
Multi-format Hardware Codec IP for High-end products

The Chips&Media's new CODA9 series - the hardware full HD encoder and decoder core, CODA966 and CODA988 - is designed to meet the strong demand for increased digital video quality, higher resolution and frame-rates for next generation multimedia applications. 

 The core is capable of decoding or encoding up to 1080p 60 frames per second enabling real-time video transcoding or communication and it can even achieve up to 4K(4Kx2K) resolution which is over four times the size of 1080p. 

The CODA9 series adds full decoding support for MVC for stereoscopic 3D experiences and Theora and WebM(VP8) for internet-connected and HTML5-enabled devices. 

     Decoder

  • ISO/IEC 14496-10 AVC(H.264) BP/MP/HP@L4.2
  • ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1
  • ISO/IEC 14496-2 MPEG-4 SP,ASP@L6
  • SMPTE 421M-2006 VC-1 SP,MP,AP@L3
  • ISO/IEC 13818-2 MPEG-2 MP@HL
  • ITU-T H.263(Annex I,J,K,T)
  • RealVideo v.8/9/10
  • AVS Jizhun @L6.2
  • AVS+ Guangdian @L6.2
  • On2 VP8
  • Sorenson Spark
  • Theora

     Encoder

  • ISO/IEC 14496-10 AVC(H.264) HP@L4.2
  • ISO/IEC 14496-2 MPEG-4 SP@L6
  • ITU-T H.263(Annex J,K,T)

     Encoding tools

  • Selective [+/-64, +/-48] Quarter-pel and half-pel accuracy motion estimation using a full-search algorithm
  • MPEG-4 AC/DC prediction
  • H.264/AVC intra-prediction
  • CABAC/CAVLC for H.264/AVC
  • In-loop deblocking filter for both H.264 and H.263
  • H.263 Annex J, K(RS=0, ASO=0) and T
  • Error resilience tools

         · Required host processor resource to run : under 1MIPS

  • Flexible Bit-rate control

         · CBR

         · VBR

         · Fixed QP

         · Low delay coding

  • Intra refresh

         · Cyclic intra refresh(CIR)

         · Motion adaptive intra refresh

  • Linear or tiled frame buffer
  • Sub frame sync. for real-time applications
  • Built-in pre rotation/mirroring function

         · 90xn degree rotation(n=0,1,2,3)

         · Vertical/horizontal mirroring

     Decoding tools

  • All variable block size supported
  • Unrestricted motion vector
  • CABAC/CAVLC for H.264/AVC
  • MPEG-4 AC/DC prediction
  • H.264/AVC intra-predictio
  • H.263 Annex I, J, K(RS=0, ASO=0) and T
  • MPEG-2 partial acceleration
  • In-loop deblocking filter for H.264, H.263, RV and AVS
  • Overlapped smoothing filter for VC-1
  • Error resilience tools

         · Resync. marker & data-partitioning with RVLC for MPEG-4

  • Linear or tiled frame buffer
  • Built-in post processing unit

         · 90xn degree rotation(n=0,1,2,3)

         · Vertical/horizontal mirroring

         · De-ringing

         · De-blocking filter for MPEG-2/MPEG-4 and DivX

  • AMBA 32-bit APB interface for communication with a host processor
  • AMBA 64-bit AXI interface for the external memory

     In half-duplex mode

  • Full HD(1080p) 30fps decoding @<133MHz>
  • Full HD(1080p) 60fps decoding @<266MHz>

     In full-duplex mode

  • HD(720p) 30fps simultaneous encoding and decoding @133MHz
  • Full HD(1080p) 30fps simultaneous encoding and decoding @266MHz

         · Required host processor resource to run : under 1MIPS

  • SmartTV
  • High-end Set-top boxes
  • Video conferenciing
  • Real-time Video Transcoding devices
  • Premium Smartphone, Tablets
  • Digital Camcorders
  • IP Cameras/Surveillance DVR
Brief Spec Down
CODA series 2.pdf
CODA_980.pdf